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cy14c512i cy14b512i, CY14E512I 512-kbit (64 k 8) serial (i 2 c) nvsram with real time clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-64879 rev. *b revised may 4, 2011 512-kbit (64 k 8) serial (i 2 c) nvsram with real time clock features 512-kbit nonvolatile static random access memory (nvsram) ? internally organized as 64 k 8 ? store to quantumtrap nonvolatile elements initiated automatically on power-down (a utostore) or by using i 2 c command (software store) or hsb pin (hardware store) ? recall to sram initiated on power-up (power-up recall) or by i 2 c command (software recall) ? automatic store on power-down with a small capacitor high reliability ? infinite read, write, and recall cycles ? 1 million store cycles to quantumtrap ? data retention: 20 years at 85 ? c real time clock (rtc) ? full-featured rtc ? watchdog timer ? clock alarm with programmable interrupts ? backup power fail indication ? square wave output with pr ogrammable frequency (1 hz, 512 hz, 4096 hz, 32.768 khz) ? capacitor or battery backup for rtc ? backup current of 0.45 a (typical) high-speed i 2 c interface ? industry standard 100 khz and 400 khz speed ? fast mode plus 1 mhz speed ? high speed 3.4 mhz ? zero cycle delay reads and writes write protection ? hardware protection using write protect (wp) pin ? software block protection for one-quarter, one-half, or entire array i 2 c access to special functions ? nonvolatile store/recall ? 8-byte serial number ? manufacturer id and product id ? sleep mode low power consumption ? average active current of 1 ma at 3.4 mhz operation ? average standby mode current of 250 a ? sleep mode current of 8 a industry standard configurations ? operating voltages: ? cy14c512i : v cc = 2.4 v to 2.6 v ? cy14b512i : v cc = 2.7 v to 3.6 v ? CY14E512I : v cc = 4.5 v to 5.5 v ? industrial temperature ? 16-pin small outline integrated circuit (soic) package ? restriction of hazardous s ubstances (rohs) compliant overview the cypress cy14c512i/cy14b 512i/CY14E512I combines a 512-kbit nvsram [1] with a full-featured rtc in a monolithic integrated circuit with serial i 2 c interface. the memory is organized as 64 k words of 8 bits each. the embedded nonvolatile elements incorporate the quantumtrap technology, creating the world?s most reliable nonvolatile memory. the sram provides infinite read and write cycles, while the quantumtrap cells provide highly reliable nonvolatile storage of data. data transfers from sram to the nonvolatile elements (store operation) takes place automatically at power-down. on power-up, data is restored to the sram from the nonvolatile memory (recall operation). the store and recall operations can also be init iated by the user through i 2 c commands. serial number 8 x 8 manufacture id/ product id memory control register command register i c control logic slave address decoder power control block control registers slave memory address and data control quantrum trap 64 k x 8 sram 64 k x 8 store sda scl a2, a1, a0 wp v cc v cap recall rtc control logic registers counters int/sqw x in x out v rtccap v rtcbat rtc slave sleep 2 memory slave note 1. serial (i 2 c) nvsram will be referred to as nvsram throughout the datasheet. logic block diagram [+] feedback www..net
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 2 of 41 contents pinout ................................................................................ 3 pin definitions .................................................................. 3 i2c interface ...................................................................... 4 protocol overview ............................................................ 4 i2c protocol ? data transfer ....................................... 4 data validity ...................................................................... 5 start condition (s) ........................................................ 5 stop condition (p) .......................................................... 5 repeated start (sr) ....................................................... 5 byte format ....................................................................... 5 acknowledge / no-acknowledge ..................................... 5 high-speed mode (hs-mode) .......................................... 6 serial data format in hs-mode ................................... 6 slave device address ...................................................... 7 memory slave device ................................................. 7 rtc registers slave device ....................................... 7 control registers slave device ................................... 7 memory control regi ster ............................................ 8 command register ..................................................... 8 write protection (wp) ....................................................... 9 autostore operation ........................................................ 9 hardware store and hsb pin operation ..................... 9 hardware recall (power up) ................................... 9 write operation ............................................................... 10 read operation ............................................................... 10 memory slave access .................................................... 10 write nvsram ........................................................... 10 current nvsram read .............................................. 12 random address read ............................................. 13 rtc registers slave access ...... .............. .............. ....... 14 write rtc registers ................................................. 14 current address rtc registers read ...................... 15 random address rtc registers read .................... 15 control registers slave ................................................. 16 write control registers ............................................. 16 current control registers read ................................ 17 random control registers read .............................. 17 serial number ................................................................. 18 serial number write .................................................. 18 serial number lock ................................................... 18 serial number read .................................................. 18 device id ......................................................................... 19 device id read ......................................................... 19 executing commands using command register ....... 19 real time clock operation ............................................ 20 nvtime operation ..................................................... 20 clock operations ....................................................... 20 reading the clock ................. .............. .............. ........ 20 setting the clock ....................................................... 20 backup power ........................................................... 20 stopping and starting the oscillator .......................... 20 calibrating the clock ................................................. 21 alarm ......................................................................... 21 watchdog timer ........................................................ 21 programmable square wave ge nerator ................... 22 power monitor ........................................................... 22 backup power monitor .......... .................................... 22 interrupts ................................................................... 22 interrupt register .. ..................................................... 22 flags register ........................................................... 23 best practices ................................................................. 29 maximum ratings ........................................................... 30 operating range ............................................................. 30 dc electrical characteristics ........................................ 30 data retention and endurance ..................................... 31 thermal resistance ........................................................ 31 ac test conditions ........................................................ 32 rtc characteristics ....................................................... 32 ac switching characteristics ....................................... 33 nvsram specifications ................................................. 34 software controlled store/recall cycles .............. 35 hardware store cycle ................................................. 36 ordering information ...................................................... 37 ordering code definitions ..... .................................... 37 package diagram ............................................................ 38 acronyms ........................................................................ 39 document conventions ................................................. 39 units of measure ....................................................... 39 document history page ................................................. 40 sales, solutions, and legal information ...................... 41 worldwide sales and design s upport ......... .............. 41 products .................................................................... 41 psoc solutions ......................................................... 41 [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 3 of 41 pinout figure 1. pin diagram - 16-pin soic pin definitions pin name i/o type description scl input clock: runs at speeds up to a maximum of f scl sda input/output i/o: input/output of data through i 2 c interface. wp input write protect: protec ts the memory from all writes. this pi n is internally pulled low and hence can be left open if not connected. a2-a0 input slave address: defines the slave address for i 2 c. these pins are internally pulled low and hence can be left open if not connected. hsb input/output hardware store busy: output: indicates busy status of nvsram when low. after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then a weak internal pull-up resistor keeps this pin hi gh (external pull-up resistor connection optional). input: hardware store implemented by pulling this pin low externally. v cap power supply autostore capacitor: supplies power to the nvsram during power loss to store data from the sram to nonvolatile elements. if not required, autostore must be disabled and this pin left as no connect. it must never be connected to ground. v rtccap power supply capacitor backup for rtc: left unconnected if v rtcbat is used. v rtcbat power supply battery backup for rtc: left unconnected if v rtccap is used. x out output crystal output connection x in input crystal input connection int/sqw output interrupt output/calibration/square wave. progra mmable to respond to the clock alarm, the watchdog timer, and the power monitor. also programmable to either active high (push or pull) or low (open drain). in calibration mode, a 512 hz square wave is driven out. in s quare wave mode, the user may select a frequency of 1 hz, 512 hz, 4096 hz, or 32768 hz to be used as a continuous output. nc no connect no connect. this pin is not connected to the die. v ss power supply ground v cc power supply power supply int/sqw wp v cap 1 2 3 4 5 6 7 8 9 10 11 12 13 nc 16 15 14 v cc a2 sda scl a1 hsb to p vi e w not to scale v rtcbat x out x in v rtccap v ss a0 [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 4 of 41 i 2 c interface i 2 c bus consists of two lines ? serial clock line (scl) and serial data line (sda) ? that carry information between multiple devices on the bus. i 2 c supports multi-master and multi-slave configurations. the data is transm itted from the transmitter to the receiver on the sda line and is synchronized with the clock scl generated by the master. the scl and sda lines are open-drain lines and are pulled up to v cc using resistors. the choice of a pull-up resistor on the system depends on the bus capaci tance and the intended speed of operation. the master gener ates the clock, and all the data i/os are transmitted in synchroni zation with this clock. the cy14x512i supports up to 3.4 mhz clock speed on scl line. protocol overview this device supports only a 7-bit addressable scheme. the master generates a start condition to initiate the communication followed by broadcasting a slave select byte. the slave select byte consists of a 7-bit slave address that the master intends to communicate with and r/w bit indicating a read or a write operation. the selected slave responds to this with an acknowledgement (ack). after a slave is selected, the remaining part of the communication takes place between the master and the selected slave device. the other devices on the bus ignore the signals on the sda line until a stop or repeated start condition is detected. the data transfer is done between the master and the selected slave device through the sda pin synchronized with the scl clock generated by the master. i 2 c protocol ? data transfer each transaction in i 2 c protocol starts with the master generating a start condition on the bus, followed by a 7-bit slave address and eighth bit (r/w ) indicating a read (1) or a write (0) operation. all signals are transmitted on the open-drain sda line and are synchronized with the clock on scl line. each byte of data transmitted on the i 2 c bus is acknowledged by the receiver by holding the sda line low on the ninth clock pulse. the request for write by the master is followed by the memory address and data bytes on the sda line. the writes can be performed in burst-mode by send ing multiple bytes of data. the memory address increments automatically after the receive/transmit of each byte on the falling edge of the ninth clock cycle. the new address is latched just prior to sending/receiving the acknowledgment bit. this allows the next sequential byte to be accessed with no additional addressing. on reaching the last memory location, the address rolls back to 0x0000 and writes continue. the slave responds to each byte sent by the master during a writ e operation with an ack. a write sequence can be terminated by the master generating a stop or repeated start condition. a read request is performed at the current address location (address next to the last location accessed for read or write). the memory slave device responds to a read request by transmitting the data on the current address location to the master. a random address read may also be performed by first sending a write request with the intended addre ss of read. the master must abort the write immediately after the last address byte and issue a repeated start or stop signal to prevent any write operation. the following read oper ation starts from this address. the master acknowledges the receipt of one byte of data by holding the sda pin low for the ninth clock pulse. the reads can be terminated by the master sending a no-acknowledge (nack) signal on the sda line after the last data byte. the nack signal causes the cy14x512i to release the sda line and the master can then generate a stop or a repeated start condition to initiate a new operation. figure 2. system configuration using serial (i 2 c) nvsram vcc sda scl vcc vcc 0 a 0 a 0 a a1 a1 a1 l c s l c s l c s sda a d s a d s p w p w p w cy14x512i cy14x512i cy14x512i #0 #1 #7 a2 a2 a2 microcontroller a2 r pmin = (v cc - v ol max) / i ol r pmax = t r / c b [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 5 of 41 data validity the data on the sda line must be stable during the high period of the clock. the state of the data line can only change when the clock on the scl line is low for the data to be valid. there are only two conditions under which the sda line may change state with scl line held high: start and stop condition. the start and stop conditions are generated by the master to signal the beginning and end of a communication sequence on the i 2 c bus. start condition (s) a high to low transition on the sda line while scl is high indicates a start condition. every transaction in i 2 c begins with the master generating a start condition. stop condition (p) a low to high transition on the sda line while scl is high indicates a stop condition. this condition indicates the end of the ongoing transaction. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again after the stop condition. repeated start (sr) if a repeated start condition is generated instead of a stop condition, the bus continues to be busy. the ongoing transaction on the i 2 c lines is stopped and the bus waits for the master to send a slave id for communication to restart. byte format each operation in i 2 c is done using 8-bit words. the bits are sent in msb first format on sda line and each byte is followed by an ack signal by the receiver. an operation continues till a nack is sent by the receiver or stop or repeated start condition is generated by the master the sda line must remain stable when the clock (scl) is high except for a start or stop condition. acknowledge / no-acknowledge after transmitting one byte of da ta or address, the transmitter releases the sda line. the receiver pulls the sda line low to acknowledge the receipt of the byte. every byte of data transferred on the i 2 c bus needs a response with an ack signal by the receiver to continue the operation. failing to do so is considered as a nack state. na ck is the state where receiver does not acknowledge the receipt of data and the operation is aborted. nack can be generated by master during a read operation in following cases: the master did not receive valid data due to noise. the master generates a nack to abort the read sequence. after a nack is issued by the master, nvsram slave releases control of the sda pin and the master is free to generate a repeated start or stop condition. nack can be generated by nvsram slave during a write operation in these cases: nvsram did not receive valid data due to noise. the master tries to access writ e protected locations on the nvsram. master must restart the communication by generating a stop or repeated start condition. figure 3. start and stop conditions figure 4. data transfer on the i 2 c bus full pagewidth sda scl p stop condition sda scl s start condition handbook, full pagewidth sr or p sda sr p scl stop or repeated start condition s or sr start or repeated start condition 1 2 3 - 8 9 ack 9 ack 78 12 msb acknowledgement signal from slave byte complete, interrupt within slave clock line held low while interrupts are serviced acknowledgement signal from receiver [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 6 of 41 high-speed mode (hs-mode) in hs-mode, nvsram can transf er data at bit rates of up to 3.4 mbit/s. a master code (0000 1xxxb) must be issued to place the device in high-speed mode. this enables master/slave communication for speeds up to 3.4 mhz. a stop condition will exit hs-mode. serial data format in hs-mode serial data transfer format in hs-mode meets the standard-mode i 2 c-bus specification. hs-mode can only commence after the following conditions (all of which are in f/s-modes): 1. start condition (s) 2. 8-bit master code (0000 1xxxb) 3. no-acknowledge bit (a ) single and multiple-byte reads and writes are supported. after the device enters into hs-mode, data transfer continues in hs-mode until stop condition is s ent by master device. the slave switches back to f/s-mode after a stop condition (p). to continue data transfer in hs-m ode, the master sends repeated start (sr). see figure 13 on page 11 and figure 16 on page 12 for hs-mode timings for read and write operation. figure 5. acknowledge on the i 2 c bus handbook, full pagewidth s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge (a) acknowledge (a) data output by master data output by slave scl from master figure 6. data transfer format in hs-mode handbook, full pagewidth f/s-mode hs-mode f/s-mode aa / a a data n (bytes + ack.) w / r s master code sr slave add. hs-mode continues sr slave add. p [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 7 of 41 slave device address every slave device on an i 2 c bus has a device select address. the first byte after start condition contains the slave device address with which the master intends to communicate. the seven msbs are the device address and the lsb (r/w bit) is used for indicating read or write operation. the cy14x512i reserves three sets of upper 4 msbs [7:4] in the slave device address field for accessing the memory, rtc registers, and control registers. the accessing mechanism is described in the following section. the nvsram product provides three different functionalities: memory, rtc registers and control registers functions (such as serial number and product id). the three functions of the device are accessed through different slave device addresses. the first four most significant bits [7:4] in the device address register are used to select between the nvsram functions. memory slave device the nvsram device is selected for read/write if the master issues the slave address as 1010b followed by three bits of device select. if the slave addre ss sent by the master matches with the memory slave device address, then depending on the r/w bit of the slave address, the data will be either read from (r/w = ?1?) or written to (r/w = ?0?) the nvsram. the address length for cy14x512i is 16 bits, and thus it requires two address bytes to map the entire memory address location. the dedicated two address bytes represent bit a0 to a15. rtc registers slave device the rtc registers is selected for read/write if the master issues the slave address as 1101b followed by three bits of device select. then, depending on the r/w bit of the slave address, data is either read from (r/w = ?1?) or written to (r/w = ?0?) the rtc registers. the rtc registers slave address is followed by one byte address of rtc register for read/write operation. the rtc registers map is explained in the ta b l e 1 0 . control registers slave device the control registers slave device includes the serial number, product id, memory control, and command register. the nvsram control register slave device is selected for read/write if the master issu es the slave address as 0011b followed by three bits of device select. then, depending on the r/w bit of the slave address, data is either read from (r/w = ?1?) or written to (r/w = ?0?) the device. table 1. slave device addressing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nvsram function select cy14x512i slave devices 1 0 1 0 device select id r/w selects memory memory, 64 k 8 1 1 0 1 device select id r/w selects rtc registers rtc registers, 16 8 0 0 1 1 device select id r/w selects control registers control registers - memory control register, 1 8 - serial number, 8 8 - device id, 4 8 - command register, 1 8 figure 7. memory slave device address handbook, halfpage r/w lsb msb slave id 10 1 0 a2 a0 a1 device select figure 8. rtc registers slave device address handbook, halfpage r/w lsb msb slave id 11 0 1 a2 a0 a1 device select [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 8 of 41 memory control register the memory control register contains the following bits: bp1:bp0 : block protect bits are used to protect 1/4, 1/2 or full memory array. these bits can be written through a write instruction to the 0x00 location of the control register slave device. however, any store cycle transfers sram data into a nonvolatile cell regardless of whether or not the block is protected. the default value sh ipped from the factory for bp0 and bp1 is ?0?. s/n lock (snl) bit : serial number lock bit (snl) is used to lock the serial number. after the bit is set to ?1?, the serial number registers are locked and no modification is allowed. this bit cannot be cleared to ?0?. the serial number is secured on the next store operation (software store or autostore). if autostore is not enabled, us er must perform the software store operation to secure the lock bit status. if a store was not performed, the serial number lock bit will not survive the power cycle. the default value sh ipped from the factory for snl is ?0?. command register the command register resides at address ?aa? of the control registers slave device. this is a write only register. the byte written to this register initiates a store, recall, autostore enable, autostore disable, and sleep mode operation as listed in table 5 . the section executing commands using command register on page 19 explains how you can execute command register bytes. store : initiates nvsram software store. the nvsram cannot be accessed for t store time after this instruction has been executed. when initiated, the device performs a store operation regardless of whether or not a write has been performed since the last nv operation. after the t store cycle time is completed, the sram is activated again for read/write operations. recall : initiates nvsram software recall. the nvsram cannot be accessed for t recall time after this instruction has been executed. the recall operation does not alter the data in the nonvolatile elements. a recall may be initiated in two ways: hardware recall, initiated on power-up; and software recall, initiated by a i 2 c recall instruction. asenb : enables nvsram autostore. the nvsram cannot be accessed for t ss time after this instruction has been executed. this setting is not nonvolatile and needs to be followed by a manual store sequence if this is desired to survive the power cycle. the part comes from the factory with autostore enabled. asdisb : disables nvsram autostore. the nvsram cannot be accessed for t ss time after this instruction has been executed. this setting is not nonvolatile and needs to be followed by a manual store sequence if this is desired to survive power cycle. note if autostore is disabled and v cap is not required, it is required that the v cap pin is left open. v cap pin must never be connected to ground. power up recall operation cannot be disabled in any case. figure 9. control registers slave device address table 2. control registers map address description read/write details 0x00 memory control register read/write contains block protect bits and serial number lock bit 0x01 serial number 8 bytes read/write (read only when snl is set) programmable serial number. locked by setting the serial number lock bit in the memory control register to ?1?. 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 device id read only device id is factory programmed 0x0a 0x0b 0x0c 0xaa command register write only allows commands for store, recall, autostore enable/disable, sleep mode table 3. memory control register bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0snl (0) 00bp1 (0) bp0 (0) 00 table 4. block protection level bp1:bp0 block protection 0 00 none 1/4 01 0xc000-0xffff 1/2 10 0x8000-0xffff 1 11 0x0000-0xffff handbook, halfpage r/w lsb msb slave id 00 1 1 a2 a0 a1 device select table 5. command register bytes data byte [7:0] command description 0011 1100 store store sram data to nonvolatile memory 0110 0000 recall recall data from nonvolatile memory to sram 0101 1001 asenb enable autostore 0001 1001 asdisb disable autostore 1011 1001 sleep enter sleep mode for low power consumption [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 9 of 41 sleep : sleep instruction puts the nvsram in a sleep mode. when the sleep instruction is registered, the nvsram performs a store operation to secure the data to nonvolatile memory and then enters into sleep mode. whenever nvsram enters into sleep mode, it initiates non volatile store cycle which results in losing an endurance cycle per sleep command execution. a store cycle starts only if a write to the sram has been performed since the last store or recall cycle. the nvsram enters into sleep mode in this manner: 1. the master sends a start command. 2. the master sends control regi sters slave device id with i 2 c write bit set (r/w = ?0?). 3. the slave (nvsram) sends an ack back to the master. 4. the master sends command register address (0xaa). 5. the slave (nvsram) sends an ack back to the master. 6. the master sends command register byte for entering into sleep mode. 7. the slave (nvsram) sends an ack back to the master. 8. the master generates a stop condition. once in sleep mode, the device starts consuming i zz current t sleep time after sleep instruction is registered. the device is not accessible for normal operations until it is out of sleep mode. the nvsram wakes up after t wake duration after the device slave address is transmitted by the master. transmitting any of the three slave addresses wakes the nvsram from sleep mode. the nvsram device is not accessible during t sleep and t wake interval and any attempt to access the nvsram device by the master is ignored and nvsram sends nack to the master. an alternate method of determining when the device is ready is for the master to send read or write commands and look for an ack. write protection (wp) the write protect (wp) pin is an active high pin and protects the entire memory and all regist ers from write operations. to inhibit all the write operations, this pin must be held high. when this pin is high, all memory and register writes are prohibited and the address counter is not incr emented. this pin is internally pulled low and, therefore, can be left open if not used. autostore operation the autostore operation is a unique feature of nvsram that automatically stores the sram data to quantumtrap cells during power-down. this store makes use of an external capacitor (v cap ) and enables the device to safely store the data in the nonvolatile memory when power goes down. during normal operation, the device draws current from v cc to charge the capacitor connected to the v cap pin. when the voltage on the v cc pin drops below v switch during power-down, the device inhibits all memory accesses to nvsram and automatically performs a conditional store operation using the charge from the v cap capacitor. the autostore operation is not initiated if no write cycle has been performed since the last store or recall. note if a capacitor is not connected to v cap pin, autostore must be disabled by issuing the autostore disable instruction specified in command register on page 8 . if autostore is enabled without a capacitor on v cap pin, the device attempts an autostore operation without suffic ient charge to complete the store. this will corrupt the data stored in nvsram as well as the serial number and it will unlock the snl bit. figure 10 shows the proper connection of the storage capacitor (v cap ) for autostore operation. see the dc electrical characteristics on page 30 for the size of the v cap . figure 10. autostore mode hardware store and hsb pin operation the hsb pin in cy14x512i is used to control and acknowledge store operations. if no store or recall is in progress, this pin can be used to request a ha rdware store cycle. when the hsb pin is driven low, the device conditionally initiates a store operation after t delay duration. an actual store cycle starts only if a write to the sram has been performed since the last store or recall cycle. re ads and writes to the memory are inhibited for t store duration or as long as hsb pin is low. the hsb pin also acts as an open drain driver (internal 100 k ? weak pull-up resistor) that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by internal 100 k ? pull-up resistor. note for successful last data byte store, a hardware store should be initiated at least one cl ock cycle after the last data bit d0 is received. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after hsb pin returns high. leave the hsb pin unconnected if not used. hardware recall (power up) during power-up, when v cc crosses v switch , an automatic recall sequence is initiated th at transfers the content of nonvolatile memory to the sram. the data may have been previously stored on the nonvolatile memory through a store sequence. 0.1 uf v cc v cap v cap v ss v cc [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 10 of 41 a power up recall cycle takes t fa time to complete and the memory access is disabled during this time. hsb pin can be used to detect the ready status of the device. write operation the last bit of the slave device a ddress indicates a read or a write operation. in case of a write operation, the slave device address is followed by the memory or register address and data. a write operation continues as long as a stop or repeated start condition is generated by the mast er or if a nack is issued by the nvsram. a nack is issued from the nvsram under the following condi- tions: 1. a valid device id is not received. 2. a write (burst write) access to a protected memory block address returns a nack from nvsram after the data byte is received. however, the address counter is set to this address and the following current read operation starts from this address. 3. a write/random read access to an invalid or out-of-bound memory address returns a nack from the nvsram after the address is received. the address counter remains unchanged in such a case. 4. a write to the command register with an invalid command. this operation returns a nack from the nvsram. after a nack is sent out from the nvsram, the write operation is terminated and any data on the sda line is ignored till a stop or a repeated start condition is generated by the master. for example, consider a case where the burst write access is performed on control register slave address 0x01 for writing the serial number and continued to the address 0x09, which is a read-only register. the device returns a nack and address counter is not incremented. a following read operation is started from the address 0x09. further, any write operation which starts from a write protected address (say, 0x09) is responded by the nvsram with a nack after the data byte is sent and set the address counter to this address. a following read operation starts from the address 0x09 in this case also. note in case you try to read/write access an address that does not exist (for example 0x0d in c ontrol register slave or 0x3f in rtc registers), nvsram responds with a nack immediately after the out-of-bound address is transmitted. the address counter remains unchanged and holds the previous successful read or write operation address. a write operation is performed internally with no delay after the eighth bit of data is transmitt ed. if a write operation is not intended, the master must term inate the write operation before the eighth clock cycle by generating a stop or repeated start condition. more details on write instructi ons are provided in the section memory slave access . read operation if the last bit of the slave device address is ?1?, a read operation is assumed and the nvsram takes control of the sda line immediately after the slave device address byte is sent out by the master. the read operation starts from the current address location (the location following the previous successful write or read operation). when the last address is reached, the address counter loops back to the first address. in case of the control register slave, whenever a burst read is performed such that it flows to a non-existent address, the reads operation loops back to 0x00. this is applicable, in particular, for the command register. read operation can be ended using the following methods: 1. the master issues a nack on the ninth clock cycle followed by a stop or a repeated start condition on the tenth clock cycle. 2. the master generates a stop or repeated start condition on the ninth clock cycle. more details on write instruct ion are provided in the section memory slave access . memory slave access the following sections describe the data transfer sequence required to perform read or write operations from nvsram. write nvsram each write operation consists of a slave address being transmitted after the start conditi on. the last bit of slave address must be set as ?0? to indicate a write operation. the master may write one byte of data or continue writing multiple consecutive address locations while the internal address counter keeps incrementing automatically. the address register is reset to 0x0000 after the last address in memory is accessed. the write operation continues till a stop or repeated start condition is generated by the master or a nack is issued by the nvsram. a write operation is executed only after nvsram receives all the eight data bits. the nvsram sends an ack signal after a successful write operation. a write operation may be terminated by the master by generating a stop condition or a repeated start operation. if the master desires to abort the current write operation without altering the memo ry contents, this should be done using a start/stop condition prior to the eighth data bit. if the master tries to access a write protected memory address on the nvsram, a nack is returned after the data byte intended to write the protected address is transmitted and address counter will not be incremented. similarly, in a burst mode write operation, a nack is returned when the data byte that attempts to write a protected memory lo cation and the address counter is not incremented. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 11 of 41 figure 11. single-byte write into nvsram (except hs-mode) s10 1 0 a2 a1 a0 0 a a a a s t a r t s t 0 p p address msb address lsb data byte memory slave address sda line by master by nvsram re 12 mtbyte rte nt nvsram eet se re 1 snebyte rte nt nvsram se re 1 mtbyte rte nt nvsram se s10 1 0 a2 a1 a0 0 a a a a s t a r t address msb address lsb data byte 1 memory slave address sda line by master a s t 0 p p data byte n ~ ~ by nvsram s00 0 0 1x x x a a a a s t a r t memory slave address address msb address lsb hs-mode command sda line by master a s t 0 p p data byte sr 10 10 a2 a1 a0 0 by nvsram s00 0 0 1x x x a a a a s t a r t memory slave address address msb address lsb hs-mode command sda line by master a data byte 1 sr 10 10 a2 a1 a0 0 a data byte 2 a data byte 3 a s t 0 p p data byte n by nvsram sda line by master by nvsram [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 12 of 41 current nvsram read each read operation starts with the master transmitting the nvsram slave address with the lsb set to ?1? to indicate ?read?. the reads start from the address on the address counter. the address counter is set to the address location next to the last accessed with a ?write? or ?read? operation. the master may terminate a read operation after reading 1 byte or continue reading addresses sequentially till the last address in the memory after which the addre ss counter roll s back to the address 0x0000. the valid methods of terminating read access are described in section read operation on page 10 . figure 15. current location single-byte nvsram read (except hs?mode) figure 16. current location multi-byte nvsram read (except hs?mode) figure 17. current location single-byte nvsram read (hs?mode) figure 18. current location multi-byte nvsram read (hs?mode) s1 0 1 0 a2 a1 a0 1 a a s t a r t s t 0 p p data byte memory slave address sda line by master by nvsram s10 1 0 a2 a1 a0 1 a a a s t a r t s t 0 p p data byte data byte n memory slave address sda line by master ~ ~ by nvsram s00 0 0 1x x x a a s t a r t memory slave address hs-mode command sda line by master s t 0 p p sr 10 10 a2 a1 a0 1 a by nvsram data byte s00 0 0 1x x x a a a s t a r t memory slave address hs-mode command sda line by master s t 0 p p sr 10 10 a2 a1 a0 1 a by nvsram data byte data byte n [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 13 of 41 random address read a random address read is performed by first initiating a write operation and generating a repeated start immediately after the last address byte is acknowledged. the address counter is set to this address and the next read access to this slave initiates read operation from here. the master may terminate a read operation after reading 1 byte or continue reading addresses sequentially till the last address in the memory after which the address counter rolls back to the start address 0x0000. figure 19. random address single-byte read (except hs?mode) figure 20. random address multi-byte read (except hs?mode) figure 21. random address single-byte read (hs?mode) s10 1 0 a2 a1 a0 0 a a a a s t a r t address msb address lsb memory slave address memory slave address sda line by master a s t 0 p p 1 01 0 a2 a1 a0 1 sr by nvsram data byte s10 1 0 a2 a1 a0 0 a a a a s t a r t address msb address lsb memory slave address memory slave address sda line by master a 1 01 0 a2 a1 a0 1 sr a s t 0 p p by nvsram data byte 1 data byte n ~ ~ s00 0 0 1x x x a a s t a r t memory slave address hs-mode command sda line by master address msb sr 10 10 a2 a1 a0 0 address lsb a memory slave address a sr 1 0 1 0 a2 a1 a0 1 s t 0 p p data byte a a by nvsram [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 14 of 41 rtc registers slave access the following sections describe the data transfer sequence required to perform read or write operations from rtc registers. write rtc registers a write to rtc registers is initiated with the rtc registers slave address followed by one byte of address and data. the master may write one byte of data or continue writing multiple consecutive address locations while the internal address counter keeps incrementing automatically. the address register is reset to 0x00 after the last rtc register is accessed. the write operation continues till a stop or repeated start condition is generated by the master or a nack is issued by the nvsram rtc registers slave. a write operation is executed only after all the eight data bits have been received by the nvsram. the nvsram sends an ack signal after the successful o peration of the wr ite instruction a write operation may be terminat ed by the master by generating a stop condition or a repeated start operation before the last data bit is sent. if the master tries to access an out of bound memory address on the rtc registers slave, a nack is returned after the address byte is transmitted. the address counter remains unaffected and the following current read operation starts from the address value held in the address counter. figure 22. random address multi-byte read (hs?mode) s00 0 0 1x x x a a s t a r t memory slave address hs-mode command sda line by master address msb sr 10 10 a2 a1 a0 0 address lsb a memory slave address a sr 1 0 1 0 a2 a1 a0 1 data byte a ~ ~ s t 0 p p data byte n a by nvsram a figure 23. single-byte write into rtc registers figure 24. multi-byte write into rtc registers s11 0 1 a2 a1 a0 0 a a a s t a r t s t 0 p p rtc register address data byte rtc registers slave address sda line by master by nvsram s11 0 1 a2 a1 a0 0 a a a s t a r t rtc register address data byte rtc registers slave address sda line by master s t 0 p p data byte n a by nvsram ~ ~ [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 15 of 41 current address rtc registers read a current read of rtc registers starts with the master sending the rtc registers slave address after the start condition. all read operations begin from the current address (the address next to previously accessed address location). after the last address is read sequentially, the address latch loops back to the first location (0x00) and read operation continues. the master may terminate a read operation after reading one byte or continue reading addresses sequentially till the last address in the memory after which the address counter rolls back to the address 0x00. a read operation may be terminated by the master by generating a stop condition or a repeated start operation or a nack. random address rtc registers read a random address read is performed by first initiating a write operation and generating a repeated start immediately after the last address byte is acknowledged. the address counter is set to this address and the next read access to this slave initiates the read operation from here. the master may terminate a read operation after reading one byte or continue reading addresses sequentially till the last address in the memory after which the address counter rolls back to the start address location of rtc (0x00). a random address read attempt on an out of bound memory address on the rtc registers slave is responded back with a nack from the nvsram after the address byte is transmitted. the address counter remains unaffected and the following current read operation starts from the address value held in the address counter. figure 25. current address rtc registers single-byte read s11 0 1 a2 a1 a0 1 a a s t a r t data byte rtc registers slave address sda line by master s t 0 p p by nvsram re 2 rrent aress r resters mtbyte rea s11 0 1 a2 a1 a0 1 a a a s t a r t data byte 1 data byte n rtc registers slave address sda line by master s t 0 p p ~ ~ by nvsram figure 27. random address rtc registers single-byte read s1 1 0 1 a2 a1 a0 0 a a a a s t a r t rtc register address rtc registers slave address rtc registers slave address sda line by master s t 0 p p 1 10 1 a2 a1 a0 1 sr data byte by nvsram re 2 ran aress r resters mtbyte rea s1 1 0 1 a2 a1 a0 0 a a a a s t a r t rtc register address rtc registers slave address sda line by master a s t 0 p p data byte n 1 10 1 a2 a1 a0 1 sr data byte 1 ~ ~ bynvsram rtc registers slave address [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 16 of 41 control registers slave the following sections describe the data transfer sequence required to perform read or write operations from control registers slave. write control registers to write the control registers sl ave, the master transmits the control registers slave address after generating the start condition. the write sequenc e continues from the address location specified by the master till the master generates a stop condition or the last writable address location. if a non-writable address location is accessed for write operation during a normal write or a burst, the slave generates a nack after the data byte is sent and the write sequence terminates. any following data bytes are ignored and the address counter is not incremented. if a write operation is performed on the command register (0xaa), the following current read operation also begins from the first address (0x00) as in this case, the current address is an out-of-bound address. the address is not incremented and the next current read operation begins from this address location. if a write operation is attemp ted on an out-of-bound address location, the nvsram sends a nack immediately after the address byte is sent. further, if the serial number is locked, only two addresses (0xaa or command register, and 0x00 or memory control register) are writable in the control regist ers slave. on a write operation to any other address location, the device will acknowledge command byte and address bytes but it returns a nack from the control registers slave for data bytes. in this case, the address will not be incremented and a current read will happen from the last acknowledged address. the nvsram control registers slave sends a nack when an out of bound memory address is accessed for write operation, by the master. in such a case, a following current read operation begins from the last acknowledged address. figure 29. single-byte write into control registers figure 30. multi-byte write into control registers s00 1 1 a2 a1 a0 0 a a a s t a r t s t 0 p p control register address data byte control registers slave address sda line by master by nvsram s00 1 1 a2 a1 a0 0 a a a a s t a r t s t 0 p p control register address data byte data byte n control registers slave address sda line by master ~ ~ by nvsram [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 17 of 41 current control registers read a read of control registers slave is started with master sending the control registers slave address after the start condition with the lsb set to ?1?. the reads begin from the current address which is the next address to the last accessed location. the reads to control registers slave continues until the last readable address location and loops back to the first location (0x00). note that the command register is a write only register and is not accessible through the sequential read operations. if a burst read operation begins from the command register (0xaa), the address counter wraps around to the first address in the register map (0x00). random control registers read a read of random address may be performed by initiating a write operation to the intended location of read and immediately following with a repeated start operation. the reads to control registers slave continues till the last readable address location and loops back to the first location (0x00). note that the command register is a write only register and is not accessible through the sequential read operat ions. a random read starting at the command register (0xaa) loops back to the first address in the control register register map (0x00). if a random read operation is initiated from an out-of-bound memory address, the nvsram sends a nack after the address byte is sent. figure 31. control registers single-byte read s00 1 1 a2 a1 a0 1 a a s t a r t s t 0 p p data byte control registers slave address sda line by master by nvsram re 2 rrent ntr resters mtbyte rea s00 1 1 a2 a1 a0 1 a a s t a r t s t 0 p p data byte data byte n control registers slave address sda line by master by nvsram a ~ ~ figure 33. random control registers single-byte read s00 1 1 a2 a1 a0 0 a a a a s t a r t s t 0 p p control register address control registers slave address data byte control registers slave address sda line by master sr 0 0 1 1 a2 a1 a0 1 by nvsram [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 18 of 41 serial number serial number is an 8 byte memory space provided to the user to uniquely identify th is device. it typically consists of a two byte customer id, followed by five bytes of unique serial number and one byte of crc check. however, nvsram does not calculate the crc and it is up to the user to utilize the eight byte memory space in the desired format. the default values for the eight byte locations are set to ?0x00?. serial number write the serial number can be accessed through the control registers slave device. to wr ite the serial number, master transmits the control registers slave address after the start condition and writes to the address location from 0x01 to 0x08. the content of serial number r egisters is secured to nonvolatile memory on the next store operation. if autostore is enabled, nvsram automatically stores the serial number in the nonvolatile memory on power-down. however, if autostore is disabled, user must perform a store operation to secure the contents of serial number registers. note if the serial number lock (snl) bit is not set, the serial number registers can be re-written regardless of whether or not a store has happened. after the serial number lock bit is set, no writes to the serial number r egisters are allowed. if the master tries to perform a write operation to the serial number registers when the lock bit is set, a nack is returned and write is not performed. serial number lock after writes to serial number regi sters is complete, the master is responsible for locking the serial number by setting the serial number lock bit to ?1? in the memory control register (0x00). the content of memory control register and serial number are secured on the next store operation (store or autostore). if autostore is not enabled, user must perform the store operation to secure the lock bit status. if a store was not performed, the serial number lock bit will not survive the power cycle. the serial number lock bit and 8-byte serial number is defaults to ?0? at power-up. serial number read serial number can be read back by a read operation of the intended address of the control registers slave. the control registers device loops back from the last address (excluding the command register) to 0x00 address location while performing burst read operation. the serial number resides in the locations from 0x01 to 0x08. even if the serial number is not locked, a serial number read operation returns the current values written to the serial number registers. the master may perform a serial number read operation to confirm if the correct serial number is written to the registers before setting the lock bit. figure 34. random control registers multi-byte read s00 1 1 a2 a1 a0 0 a a a s t a r t control register address control registers slave address data byte control registers slave address sda line by master sr 0 0 1 1 a2 a1 a0 1 a s t 0 p p data byte n a ~ ~ by nvsram [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 19 of 41 device id device id read device id is a 4-byte code consisting of jedec assigned manufac turer id, product id, density id, and die revision. these regist ers are set in the factory and are r ead only registers for the user. the device id is divided into four parts as shown in table 6 : 1. manufacturer id (11 bits) this is the jedec assigned manufacturer id for cypress. jedec assigns the manufacturer id in different banks. the first three bits of the manufacturer id represent the bank in which id is assigned. the next eight bits represent the manufacturer id. cypress manufacturer id is 0x34 in bank 0. therefore the manufacturer id for all cypress nvsram products is as given below: cypress id - 000_0011_0100 2. product id (14 bits) the product id for device is shown in the ta b l e 6 . 3. density id (4 bits) the 4-bit density id is used as shown in table 6 for indicating the 512 kb density of the product. 4. die rev (3 bits) this is used to represent any major change in the design of the product. the initial setting of this is always 0x0. executing commands using command register the control registers slave allows different commands to be executed by writing the specific command byte in the command register (0xaa). the command byte codes for each command are specified in ta b l e 5 . during the execution of these commands the device is not accessible and returns a nack if any of the three slave devices is selected. if an invalid command is sent by the master, nvsram responds with a nack indicating that the command was not successf ul. the address latch of this slave continues to point to the command register address. table 6. device id bits #of bits 31 - 21 (11 bits) 20 - 7 (14 bits) 6 - 3 (4 bits) 2 - 0 (3 bits) device manufacturer id product id density id die rev cy14c512i 00000110100 00001111000001 0011 000 cy14b512i 00000110100 00001111010001 0011 000 CY14E512I 00000110100 0000 1111100101 0011 000 figure 35. command execution using command register s00 1 1 a2 a1 a0 0 a a s t a r t command register address command byte control register slave address sda line by master a 1 0 0 0 0 1 1 1 by nvsram p s t o p [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 20 of 41 real time clock operation nvtime operation the cy14x512i offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. the rtc registers occupy a separate address space from nvsram and are accessible through the read rtc register and write rtc register sequence on register addresses 0x00 to 0x0f. internal double buffering of the clock and the timer information registers prevents accessing transitional internal clock data during a read or write operation. double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. clock and alarm registers store data in bcd format. clock operations the clock registers maintain time up to 9,999 years in one-second increments. the time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and cent ury transitions. there are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. these registers contain the time of day in bcd format. bits defined as ?0? are currently not used and are reserved for future use by cypress. reading the clock the double buffered rtc register structure reduces the chance of reading incorrect data from the clock. stop internal updates to the cy14x512i time keeping regi sters before reading clock data to prevent reading of data in transition. stopping the register updates does not affect clock accuracy. when an read sequence of rtc device is initiated, the update of the user timekeeping register s stops and does not restart until a stop or a repeated start condition is generated. the rtc registers are read while the internal clock continues to run. after the end of read sequence, all the rtc registers are simultaneously updated within 20 ms. setting the clock a write access to the rtc device stops updates to the time keeping registers and enables the time to be set. the correct day, date, and time is then written into the registers and must be in 24 hour bcd format. the time written is referred to as the ?base time?. this value is stored in nonvolatile registers and used in the calculation of the current time. when a stop or a repeated start condition is encountered, the values of timekeeping registers are transferred to the actual clock counters after which the clock resumes normal operation. if a valid stop or repeated start condition is not generated by the master, the time written to the rtc registers is never trans- ferred to the actual clock counters. if the time written to the timekeeping registers is not in the correct bcd format, each invalid nibble of the rtc registers continue counting to 0xf before rolling over to 0x0 after which rtc resumes normal operation. note after ?w? bit is set to ?0?, valu es written into the timekeeping, alarm, calibration, and interrupt registers are transferred to the rtc time keeping counters in t rtcp time. these counter values must be saved to nonvolatile memory either by initiating a software/hardware store or autostore operation. while working in autostore disabled mode, perform a store operation after t rtcp time while writing into the rtc registers for the modifications to be correctly recorded. backup power the rtc in the cy14x512i is intended for permanently powered operation. the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when the primary power, v cc , fails and drops below v switch the device switches to the backup power supply. the clock oscillator uses very little current, which maximizes the backup time available from the backup source. regardless of the clock operation with the primary source removed, the data stored in the nvsram is secure, having been stored in the nonvolatile elements when power was lost. during backup operation, the cy14x512i consumes a 0.45 a (typ) at room temperature. the user must choose capacitor or battery values according to the application. backup time values based on maximum current specifications are shown in the following table. nominal backup times are approximately two times longer. using a capacitor has the obvious advantage of recharging the backup source each time the syst em is powered up. if a battery backup is used, a 3-v lithium battery is recommended and the cy14x512i sources current only from the battery when the primary power is removed. however, the battery is not recharged at any time by the cy14x512i. the battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. stopping and starting the oscillator the oscen bit in the calibration register at 0x08 controls the enable and disable of the oscillator. this bit is nonvolatile and is shipped to customers in the ?e nabled? (set to ?0?) state. to preserve the battery life when t he system is in storage, oscen must be set to ?1?. this turns of f the oscillator circuit, extending the battery life. if the oscen bit goes from disabled to enabled, it takes approximately one se cond (two seconds maximum) for the oscillator to start. while system power is off, if the voltage on the backup supply (v rtccap or v rtcbat ) falls below their resp ective minimum level, the oscillator may fail.the cy14 x512i has the ability to detect oscillator failure when system powe r is restored. this is recorded in the oscillator fail flag (oscf) of the flags register at the address 0x00. when the device is powered on (v cc goes above v switch ) the oscen bit is checked for the ?enabled? status. if the oscen bit is enabled and the oscillator is not active within the first 5 ms, the oscf bit is se t to ?1?. the system must check for this condition and then write ?0? to clear the flag. table 7. rtc backup time capacitor value backup time (cy14b512i) 0.1f 60 hours 0.47f 12 days 1.0f 25 days [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 21 of 41 note that in addition to setting the oscf flag bit, the time registers are reset to the ?bas e time? (when a read sequence of the rtc device is initiated, the update of the user timekeeping registers stops and does not restart until a stop or a repeated start condition is generated. the rtc registers are read while the internal clock continues to run. after the end of read sequence, all the rtc regist ers are simultaneously updated within 20 ms.), which is the value last written to the timekeeping registers. the control or calibration registers and the oscen bit are not affected by the ?oscillator failed? condition. the value of oscf must be reset to ?0? when the time registers are written for the first time. this initializes the state of this bit which may have become set when the system was first powered on. to reset oscf, set the write bit ?w? (in the flags register at 0x00) to a ?1? to enable writes to the flags register. write a ?0? to the oscf bit and then reset the write bit to ?0? to disable writes. calibrating the clock the rtc is driven by a quartz-controlled crystal with a nominal frequency of 32.768 khz. clock accuracy depends on the quality of the crystal and calibration. the crystals available in the market typically have an error of + 20 ppm to + 35 ppm. however, cy14x512i employs a calibration circuit that improves the accuracy to +1/?2 ppm at 25 c. this implies an error of +2.5 seconds to -5 seconds per month. the calibration circuit adds or subt racts counts from the oscillator divider circuit to achieve this accuracy. the number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the calibration register at 0x08. the calibration bits occupy the five lo wer order bits in the calibration register. these bits are set to represent any value between ?0? and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibration and a ?0? indicates negative calibration. adding counts speeds the clock up and subtracting counts slows the clock down. if a binary ?1? is loaded into the register, it corresponds to an adjustment of 4.068 or ?2.034 ppm offset in oscillator error, depending on the sign. calibration occurs within a 64-minute cycl e. the first 62 minutes in the cycle may, once per minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. if a binary ?1? is loaded into the register, only the first two minutes of the 64-minute cycle are modified. if a binary 6 is loaded, the first 12 are affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles , that is, 4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. to determine the required calibration, the cal bit in the flags register (0x00) must be set to ?1?. this causes the int pin to toggle at a nominal frequency of 512 hz. any deviation measured from the 512 hz indica tes the degree and direction of the required correction. for ex ample, a reading of 512.01024 hz indicates a +20 ppm error. hence, a decimal value of ?10 (001010b) must be loaded into the calibration register to offset this error. note setting or changing the calibration register does not affect the test output frequency. to set or clear cal, set the write bit ?w? (in the flags register at 0x00) to ?1? to enable writes to the flags register. write a value to cal, and then reset the write bit to ?0? to disable writes. alarm the alarm function compares user programmed values of alarm time and date (stored in the registers 0x01-5) with the corresponding time of day and date values. when a match occurs, the alarm internal flag (af) is set and an interrupt is generated on int pin if alarm interrupt enable (aie) bit is set. there are four alarm match fields - date, hours, minutes, and seconds. each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field is used in the match process. depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. selecting all match bits (all 0s) causes an exact time and date match. there are two ways to detect an alarm event: by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x00 indicates that a date or time match has occurred. the af bit is set to ?1? when a match occurs. reading the flags register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. to set, clear or enable an alarm, set the ?w? bit (in flags register - 0x00) to ?1? to enable writes to alarm registers. after writing the alarm value, clear the ?w? bit back to ?0? for the changes to take effect. note cy14x512i requires the alarm match bit for seconds (0x02 - d7) to be set to ?0? for proper operation of alarm flag and interrupt. watchdog timer the watchdog timer is a free running down counter that uses the 32 hz clock (31.25 ms) derived fr om the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the timer consists of a loadable register and a free running counter. on power-up, the watchdog time out value in register 0x07 is loaded into the counter load register. counting begins on power-up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to ?1?. the counter is compared to the terminal value of ?0?. if the counter reaches this value, it causes an internal flag and an optional interrupt output. you can prevent the time out interrupt by setting wds bit to ?1? prior to the counter reaching ?0?. this caus es the counter to reload with the watchdog time out value and to be restarted. as long as the user sets the wds bit prior to the counter reaching the terminal value, the interrupt and wdt flag never occur. new time out values are written by setting the watchdog write bit to ?0?. when the wdw is ?0?, new writes to the watchdog time out value bits d5-d0 are enabled to modify the time out value. when wdw is ?1?, writes to bits d5-d0 are ignored. the wdw function enables a user to set the wds bit without concern that the watchdog timer value is modified. a logical diagram of the watchdog timer is shown in figure 36 on page 22 . note that [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 22 of 41 setting the watchdog time out value to ?0? disables the watchdog function. the output of the watchdog timer is the flag bit wdf that is set if the watchdog is allowed to time out. if the watchdog interrupt enable (wie) bit in the interrupt register is set, a hardware interrupt on int pin is also generated on watchdog timeout. the flag and the hardware interrupt are both cleared when user reads the flag registers. . programmable square wave generator the square wave generator block uses the crystal output to generate a desired frequency on the int pin of the device. the output frequency can be programmed to be one of the following: 1. 1 hz 2. 512 hz 3. 4096 hz 4. 32768 hz the square wave output is not generated while the device is running on backup power. power monitor the cy14x512i provides a power management scheme with power fail interrupt capability. it also controls the internal switch to back up power for the clock and protects the memory from low v cc access. the power monitor is based on an internal band gap reference circuit that compares the v cc voltage to v switch threshold. when v switch is reached , as v cc decays from power loss, a data store operation is initiate d from sram to the nonvolatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source, read and write operations to nvsram are inhibited and the rtc functions are not available to the user. the rtc clock continues to operate in the background. the updated rt c time keeping registers are available to the user after v cc is restored to the device (see nvsram specifications on page 34 ). backup power monitor the cy14x512i provides a ba ckup power monitoring system that detects the backup power (either battery or capacitor backup) failure. the backup power fail flag (bpf) is issued on the next power-up in case of backup power failure. the bpf flag is set in the event of backup voltage falling lower than v bakfail . the backup power is monitored even while the rtc is running in backup mode. low voltage detected during backup mode is flagged through the bpf flag. bpf can hold the data only until a defined low level of the back up voltage (v dr ). interrupts the cy14x512i has a flags register, interrupt register, and interrupt logic that can signal interrupt to the microcontroller. there are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. each of these can be individually enabled to drive the int pin by appropriate setting in the interrupt register (0x06). in addition, each has an associated flag bit in the flags register (0x00) that the host processor uses to determine the cause of the interrupt. the int pin driver has two bits that specify its behavior when an interrupt occurs. an interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in interrupts register is enabled (set to ?1?). after an interrupt source is active, two programmable bits, h/l and p/l, determine the behavior of the output pin driver on int pin. these two bits are located in the interrupt register and can be used to drive level or pulse mode output from the int pin. in pulse mode, the pulse width is internally fixed at approximatel y 200 ms. this mode is intended to reset a host microcontroller. in the level mode, the pin goes to its active polarity until the flags register is read by the user. this mode is used as an interrupt to a host microcontroller. the control bits are summarized in the following section. interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. note cy14x512i generates valid interrupts only after the powerup recall sequence is completed. all events on int pin must be ignored for t fa duration after powerup. interrupt register watchdog interrupt enable (wie): when set to ?1?, the watchdog timer drives the int pin and an internal flag when a watchdog time out occurs. when wie is set to ?0?, the watchdog timer only affects the wdf flag in flags register. alarm interrupt enable (aie) : when set to ?1?, the alarm match drives the int pin and an internal flag. when aie is set to ?0?, the alarm match only affects the af flag in the flags register. power fail interrupt enable (pfe): when set to ?1?, the power fail monitor drives the pin and an internal flag. when pfe is set to ?0?, the power fail monitor only affects the pf flag in the flags register. square wave enable (sqwe): when set to ?1?, a square wave of programmable frequency is generated on the int pin. the frequency is decided by the sq1 and sq0 bits of the interrupts register. this bit is nonvolatile and survives power cycle. the sqwe bit overrides all other interrupts. however, cal bit will take precedence over the squar e wave generator. this bit defaults to ?0? from the factory. figure 36. watchdog timer block diagram 1 hz oscillator clock divider counter zero compare wdf wds load register wdw d q q watchdog register write to watchdog register 32 hz 32.768 khz [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 23 of 41 high/low (h/l) : when set to a ?1?, the int pin is active high and the driver mode is push pull. the int pin drives high only when v cc is greater than v switch . when set to a ?0?, the int pin is active low and the drive mode is open drain. the int pin must be pulled up to vcc by a 10 k resistor while using the interrupt in active low mode. pulse/level (p/l): when set to a ?1? and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/l is set to a ?0?, the int pin is driven high or low (determined by h/l) until the flags register is read. sq1 and sq0 . these bits are used together to fix the frequency of square wave on int pin output when sqwe bit is set to ?1?. these bits are nonvolatile and survive power cycle. the output frequency is decided as illustrated in this table. when an enabled interrupt source activates the int pin, an external host reads the flag registers to determine the cause. remember that all flags are clea red when the register is read. if the int pin is programmed for level mode, then the condition clears and the int pin returns to its inactive state. if the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. the pulse does not complete its specified duration if the flags register is read. if the int pin is used as a host reset, the flags register is not read during a reset. following is a summary table that shows the state of the int pin. flags register the flags register has three flag bits: wdf, af, and pf, which can be used to generate an interrupt. these flags are set by the watchdog timeout, alarm match, or power fail monitor respectively. the processor can either poll this register or enable interrupts to be informed when a flag is set. these flags are automatically reset after the regist er is read. the flags register is automatically loaded with the value 0x00 on power-up (except for the oscf bit. see stopping and starting the oscillator on page 20 ). table 8. sqw output selection sq1 sq0 frequency comment 0 0 1 hz 1 hz signal 0 1 512 hz 512 hz clock output 1 0 4096 hz 4 khz clock output 1 1 32768 hz oscillator output frequency table 9. state of the int pin cal sqwe wie/aie/ pfe int pin output 1 x x 512 hz 0 1 x square wave output 00 1 alarm 00 0 hi-z [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 24 of 41 figure 37. rtc recommended component configuration figure 38. interrupt block diagram recommended values y1 = 32.768 khz (12.5 pf) c 1 = 12 pf c 2 = 69 pf x out x in y1 c2 c1 note the recommended values for c1 and c2 include board trace capacitance. wdf - watchdog timer flag wie - watchdog interrupt pf - power fail flag pfe - power fail enable af - alarm fag aie - alarm interrupt enable p/l - pulse level h/l - high/low enable pin driver wie wdf watchdog timer pfe pf aie af clock alarm p/l h/l v cc v ss int sqwe cal mux 512 hz clock square wave priority encoder wie/pie/ aie hi-z control sel line power monitor sqwe - square wave enable [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 25 of 41 table 10. rtc register map [2, 3] register bcd format data function/range d7 d6 d5 d4 d3 d2 d1 d0 0x0f 10s years years years: 00?99 0x0e 0 0 0 10s months months months: 01?12 0x0d 0 0 10s day of month day of month day of month: 01?31 0x0c 0 0 0 0 0 day of week day of week: 01?07 0x0b 0 0 10s hours hours hours: 00?23 0x0a 0 10s minutes minutes minutes: 00?59 0x09 0 10s seconds seconds seconds: 00?59 0x08 oscen (0) 0cal sign (0) calibration (00000) calibration values [4] 0x07 wds (0) wdw (0) wdt (000000) watchdog [4] 0x06 wie (0) aie (0) pfe (0) sqwe (0) h/l (1) p/l (0) sq1 (0) sq0 (0) interrupts [4] 0x05 m (1) 0 10s alarm date alarm day alarm, day of month: 01?31 0x04 m (1) 0 10s alarm hours alarm hours alarm, hours: 00?23 0x03 m (1) 10s alarm minutes alarm minutes alarm, minutes: 00?59 0x02 m (1) 10s alarm seconds alarm seconds alarm, seconds: 00?59 0x01 10s centuries centuries centuries: 00?99 0x00 wdf af pf oscf [5] bpf [5] cal (0) w (0) r (0) flags [4] notes 2. ( ) designates values shipped from the factory. 3. the unused bits of rtc registers are reserved for future use and should be set to ?0? 4. this is a binary value, not a bcd value. 5. when user resets oscf and bpf flag bi ts, the flags register will be updated after t rtcp time. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 26 of 41 table 11. register map detail register description 0x0f time keeping - years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of t he year. lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0?99. 0x0e time keeping - months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibble (four bits ) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operate s from 0 to 1. the range for the register is 1?12. 0x0d time keeping - date d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower ni bble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operat es from 0 to 3. the range for the register is 1?31. leap years are automatically adjusted for. 0x0c time keeping - day d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble (three bits) contains a value that correlates to day of the week. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, beca use the day is not integrated with the date. 0x0b time keeping - hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s hours hours contains the bcd value of hours in 24 hour format. lower ni bble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the r ange for the register is 0?23. 0x0a time keeping - minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and oper ates from 0 to 5. the range for the register is 0?59. 0x09 time keeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble (four bits ) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operat es from 0 to 5. the range for the register is 0?59. 0x08 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to ?1?, t he oscillator is stopped. when set to ?0?, the oscillator runs. disabling the oscilla tor saves battery or capacitor power during storage. calibration sign determines if the calibration adjustment is applied as an a ddition (1) to or as a subtraction (0) from the time-base. calibration these five bits control the calibration of the clock. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 27 of 41 0x07 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to ?1? reloads and restarts the watchdog timer. setting the bit to ?0? has no effect. the bit is cleared automatically after the watchdog timer is rese t. the wds bit is write only. reading it always returns a 0. wdw watchdog write enable. setting this bit to ?1? disables any write to the watchdog timeout value (d5?d0). this enables the user to set the watchdog strobe bit without disturbing the ti meout value. setting this bit to ?0? allows bits d5?d0 to be written to the watchdog regist er when the next write cycle is complete. this function is explained in more detail in watchdog timer on page 21 . wdt watchdog timeout selection. the watchdog timer interval is se lected by the 6-bit value in this register. it represents a multiplier of the 32 hz count (31.25 ms). the range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 fh). setting the watchdog timer register to ?0? disables the timer. these bits can be written only if the wdw bit was set to 0 on a previous cycle. 0x06 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfe sqwe h/l p/l sq1 sq0 wie watchdog interrupt enable. when set to ?1? and a watchdog timeout occurs, the watchdog timer drives the int pin and the wdf flag. when set to ?0?, the watc hdog timeout affects only the wdf flag. aie alarm interrupt enable. when set to ?1?, the alarm match drives the int pin and t he af flag. when set to ?0?, the alarm match only affects the af flag. pfe power fail enable. when set to ?1?, the alarm match drives the int pin and the pf flag. when set to ?0?, the power fail monitor affects only the pf flag. sqwe square wave enable. when set to ?1?, a square wave is driven on the int pin with frequency programmed using sq1 and sq0 bits. the square wave output takes precedence over in terrupt logic. if the sqwe bit is set to ?1?. when an enabled interrupt source becomes active, only the corresponding flag is raised and the int pin continues to drive the square wave. h/l high/low. when set to ?1?, the int pin is driven active hi gh. when set to ?0?, the int pin is open drain, active low. p/l pulse/level. when set to ?1?, the int pi n is driven active (determined by h/l) by an interrupt source for approximately 200 ms. when set to ?0?, the int pin is driven to an active level (as set by h/l) until the flags register is read. sq1, sq0 sq1, sq0. these bits are used to decide the frequen cy of the square wave on the int pin output when sqwe bit is set to ?1?. the following is the frequency output for each combination of (sq1, sq0): (0, 0) - 1 hz (0, 1) - 512 hz (1, 0) - 4096 hz (1, 1) - 32768 hz 0x05 alarm - day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to select or deselect the date value. m match. when this bit is set to ?0?, the date value is used in the alarm match. setting this bi t to ?1? causes the match circui t to ignore the date value. 0x04 alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the ma sk bit to select or de select the hours value. m match. when this bit is set to ?0?, the hours value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the hours value. table 11. register map detail (continued) register description [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 28 of 41 0x03 alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm minutes alarm minutes contains the alarm value for the minutes and the ma sk bit to select or deselect the minutes value. m match. when this bit is set to ?0?, the minutes value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the minutes value. 0x02 alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm seconds alarm seconds contains the alarm value for the seconds and the ma sk bit to select or deselect the seconds? value. m match. when this bit is set to ?0?, the seconds value is used in the alarm match. setting this bit to ?1? causes the match circuit to ignore the seconds value. 0x01 time keeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 10s centuries centuries contains the bcd value of centuries. lower nibble contai ns the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. the range for the register is 0-99 centuries. 0x00 flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf bpf cal w r wdf watchdog timer flag. this read only bit is set to ?1? when the watchdog timer is allowed to reach ?0? without being reset by the user. it is cleared to ?0? when the flags register is read or on power-up af alarm flag. this read only bit is set to ?1? when the time and date match the values stored in the alarm registers with the match bits = ?0?. it is cleared when the flags register is read or on power-up. pf power fail flag. this read only bit is set to ?1? when power falls below the power fail threshold v switch . it is cleared when the flags register is read. oscf oscillator fail flag. set to ?1? on power-up if the oscillator is enabled and not running in the first 5 ms of operation. t his indicates that rtc backup power failed and clock value is no longer valid. this bit survives power cycle and is never cleared internally by the chip. the user must check for this condition and write '0' to clear this flag. when user resets oscf flag bit, the bit will be updated after t rtcp time. bpf backup power fail flag. set to ?1? on power-up if the backup power (battery or capacitor) failed. the backup power fail condition is determined by the voltage falling below their re spective minimum specified voltage. bpf can hold the data only till a defined low level of the back up voltage (v dr ). user must reset this bit to clear this flag. when user resets bpf flag bit, the bit will be updated after t rtcp time. cal calibration mode. when set to ?1?, a 512 hz square wave is output on the int pin. when se t to ?0?, the int pin resumes normal operation. this bit takes priority than sq0/sq1 and ot her functions. this bit defaults to ?0? (disabled) on power-up. w write enable: setting the ?w? bit to ?1? freezes updates of t he rtc registers. the user can then write to rtc registers, alarm registers, calibration register, inte rrupt register and flags register. setting the ?w? bit to ?0? causes the contents of the rtc registers to be transferred to the time keeping counte rs if the time has changed. this transfer process takes t rtcp time to complete. this bit defaults to 0 on power-up. r read enable: setting ?r? bit to ?1?, stops clock updates to us er rtc registers so that clock updates are not seen during the reading process. set ?r? bit to ?0? to resume clock updates to the holding register. setting this bit does not require ?w? bit to be set to ?1?. this bit defaults to ?0? on power-up. table 11. register map detail (continued) register description [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 29 of 41 best practices nvsram products have been used effectively for over 26 years. while ease-of-use is one of t he product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in this nvsram product are delivered by cypress with 0x00 written in all cells. incoming inspection routines at customer or c ontract manufacturer?s sites sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique nv pattern (that is, complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. power up boot firmware routines should rewrite the nvsram into the desired state (for example, autostore enabled). while the nvsram is shipped in a pres et state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. the v cap value specified in this datasheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the maximum v cap value because the nvsram internal algorithm calculates v cap charge and discharge time based on this max v cap value. customers that want to use a larger v cap value to make sure there is extra store charge and store time should discuss their v cap size selection. when base time is updated, th ese updates are transferred to the time keeping registers when ?w? bit is set to ?0?. this transfer takes t rtcp time to complete. it is recommended to initiate software store or hardware store after t rtcp time to save the base time into nonvolatile memory. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 30 of 41 maximum ratings exceeding maximum ratings may s horten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c maximum accumulated storage time at 150 ? c ambient temperature ....................... 1000 h at 85 ? c ambient temperature ..................... 20 years ambient temperature with power applied ..... .............. .............. .......... ?55 ? c to +150 ? c supply voltage on v cc relative to v ss cy14c512i: v cc = 2.4 v to 2.6 v......?0.5 v to +3.1 v cy14b512i: v cc = 2.7 v to 3.6 v ......?0.5 v to +4.1 v CY14E512I: v cc = 4.5 v to 5.5 v ......?0.5 v to +7.0 v dc voltage applied to outputs in high z state...................................... ?0.5 v to v cc + 0.5 v input voltage ........................................ ?0.5 v to v cc + 0.5 v transient voltage (<20 ns) on any pin to ground potential .................. ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) .................................................. 1.0 w surface mount lead soldering temperature (3 seconds) ......... .............. .............. ..... +260 ? c dc output current (1 output at a time, 1s duration). .... 15 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch up current..................................................... > 140 ma operating range product range ambient temperature v cc cy14c512i industrial ?40 ? c to +85 ? c 2.4 v to 2.6 v cy14b512i 2.7 v to 3.6 v CY14E512I 4.5 v to 5.5 v dc electrical characteristics over the operating range parameter description test conditions min typ [6] max unit v cc power supply cy14c512i 2.4 2.5 2.6 v cy14b512i 2.7 3.0 3.6 v CY14E512I 4.5 5.0 5.5 v i cc1 average v cc current f scl = 3.4 mhz; values obtained without output loads (i out = 0 ma) ??1ma i cc2 average v cc current during store all inputs don?t care, v cc = max average current for duration t store ??2ma i cc3 average v cc current f scl = 100 khz; v cc = v cc (typ), 25 c all inputs cycling at cmos levels. values obtained without output loads (i out = 0 ma) ??1ma i cc4 average v cap current during autostore cycle all inputs don't care. average current for duration t store ??3ma i sb v cc standby current scl > (v cc ? 0.2 v). v in < 0.2 v or > (v cc ? 0.2 v). ?w? bit set to ?0?. standby current level after nonvolatile cycle is complete. inputs are static. f scl = 0 mhz. ??250 ? a i zz sleep mode current t sleep time after sleep instruct ion is registered. all inputs are static and configured at cmos logic level. ??8 ? a i ix [7] input current in each i/o pin (except hsb ) 0.1 v cc < v i < 0.9 v cc max ?1 ? +1 ? a input current in each i/o pin (for hsb ) ?100 ? +1 ? a i oz output leakage current ?1 ? +1 ? a c i capacitance for each i/o pin capacitance measured across all input and output signal pin and v ss . ??7pf notes 6. typical values are at 25 c, v cc = v cc (typ). not 100% tested. 7. not applicable to wp, a2, a1 and a0 pins. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 31 of 41 v ih input high voltage 0.7 vcc ? v cc + 0.5 v v il input low voltage ? 0.5 ? 0.3 v cc v v ol output low voltage i ol = 3 ma 0 ? 0.4 v r in [8] input resistance (wp, a2, a1, a0) for v in = v il (max) 50 ? ? k ? for v in = v ih (max) 1??m ? v hys hysteresis of schmitt trigger inputs 0.05 v cc ??v v cap storage capacitor between v cap pin and v ss cy14c512i 170 220 270 ? f cy14b512i CY14E512I 42 47 180 ? f dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [6] max unit data retention and endurance parameter description min unit data r data retention 20 years nv c nonvolatile store operations 1,000 k thermal resistance parameter [9] description test conditions 16-pin soic unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, according to eia / jesd51. 56.68 ? c/w ? jc thermal resistance (junction to case) 32.11 ? c/w notes 8. the input pull-down circuit is stronger (50 k ? ) when the input voltage is below v il and weak (1 m ? ) when the input voltage is above v ih . 9. these parameters are guaranteed by design and are not tested. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 32 of 41 figure 39. ac test loads and waveforms ac test conditions description cy14c512i cy14b512i CY14E512I input pulse levels 0 v to 2.5 v 0 v to 3 v 0 v to 5 v input rise and fall times (10% - 90%) 10 ns 10 ns 10 ns input and output timing reference levels 1.25 v 1.5 v 2.5 v rtc characteristics parameters description min typ max units v rtcbat rtc battery pin voltage 1.8 ? 3.6 v i bak [10] rtc backup current ?0.450.6a v rtccap [11] rtc capacitor pin voltage 1.6 ? 3.6 v v bakfail backup failure threshold 1.8 ? 2 v v dr bpf flag retention voltage 1.6 ? ? v t ocs rtc oscillator time to start ? 1 2 sec t rtcp rtc processing time from end of ?w? bit set to ?0? ? ? 1 ms r bkchg rtc backup capacitor charge current-limiting resistor 350 ? 850 ? 2.5 v output 100 pf 700 ? for 2.5 v (cy14c512i) 3.0 v output 100 pf 867 ? for 3.0 v (cy14b512i) 5.0 v output 50 pf 1.6 k ? for 5.0 v (CY14E512I) notes 10. current drawn from either v rtccap or v rtcbat when v cc < v switch. 11. if v rtccap > 0.5 v or if no capacitor is connected to v rtccap pin, the oscillator will start in tocs time. if a backup capacitor is connected and v rtccap < 0.5 v, the capacitor must be allowed to char ge to 0.5 v for oscillator to start. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 33 of 41 ac switching characteristics parameter description 3.4 mhz [12] 1 mhz [12] 400 khz [12] unit min max min max min max f scl clock frequency, scl ? 3400 ? 1000 ? 400 khz t su; sta setup time for repeated start condition 160 ? 250 ? 600 ? ns t hd;sta hold time for start condition 160 ? 250 ? 600 ? ns t low low period of the scl 160 ? 500 ? 1300 ? ns t high high period of the scl 60 ? 260 ? 600 ? ns t su;data data in setup time 10 ? 100 ? 100 ? ns t hd;data data hold time (in/out) 0 ? 0 ? 0 ? ns t dh data out hold time 0 ? 0 ? 0 ? ns t r [13] rise time of sda and scl ? 80 ? 120 ? 300 ns t f [13] fall time of sda and scl ? 80 ? 120 ? 300 ns t su;sto setup time for stop condition 160 ? 250 ? 600 ? ns t vd;data data output valid time ? 130 ? 400 ? 900 ns t vd;ack ack output valid time ? 130 ? 400 ? 900 ns t of [13] output fall time from v ih min to v il max ? 80 ? 120 ? 300 ns t buf bus free time between stop and next start condition 0.3 ? 0.5 ? 1.3 ? us t sp pulse width of spikes that must be suppressed by input filter ?5?50?50ns figure 40. ti ming diagram ~ ~ ~ ~ s sr t su;sto t su;sta t hd;sta t high t low t su;data t hd;data sda scl p s t buf t sp t hd;sta ~ ~ ~ ~ ~ ~ ~ ~ t r t f t f t r note 12. (bus load capacitance (cb) c onsiderations; cb < 500 pf for i 2 c clock frequency (scl) 100/400/1000 khz; cb <100 pf for scl at 3.4 mhz). 13. these parameters are guaranteed by design and are not tested. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 34 of 41 nvsram specifications parameter description min max unit t fa [14] power-up recall duration cy14c512i ? 40 ms cy14b512i ? 20 ms CY14E512I ? 20 ms t store [15] store cycle duration ? 8 ms t delay [16] time allowed to complete sram write cycle ? 25 ns t vccrise [17] v cc rise time 150 ? s v switch low voltage trigger level cy14c512i ? 2.35 v cy14b512i ? 2.65 v CY14E512I ? 4.40 v t lzhsb [17] hsb high to nvsram active time ? 5 s v hdis [17] hsb output disable voltage ? 1.9 v t hhhd [17] hsb high active time ? 500 ns t wake time for nvsram to wake up from sleep mode cy14c512i ? 40 ms cy14b512i ? 20 ms CY14E512I ? 20 ms t sleep time to enter low power mode af ter issuing sleep instruction ? 8 ms t sb time to enter into standby mode after issuing stop condition ? 100 s figure 41. autostor e or power-up recall [18] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t fa t fa hsb out autostore power- up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note note v cc 15 15 19 19 notes 14. t fa starts from the time v cc rises above v switch. 15. if an sram write has not taken place since the last nonvolatile cycle, no autostore or hardware store takes place. 16. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 17. these parameters are guaranteed by design and are not tested. 18. read and write cycles are ignored during store, recall, and while v cc is below v switch. 19. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 35 of 41 software controlled store/recall cycles parameter description cy14x512i unit min max t recall recall duration ? 600 s t ss [20, 21] software sequence processing time ? 500 s figure 42. software store/recall cycle [21] figure 43. autostore enable/disable cycle s start condition 9 8 2 1 acknowledge (a) by slave data output by master scl from master 9 8 2 1 9 8 2 1 nvsram control slave address command reg address command byte (store/recall) p stop condition store t rwi / recall t acknowledge (a) by slave acknowledge (a) by slave s start condition 9 8 2 1 acknowledge (a) by slave data output by master scl from master 9 8 2 1 9 8 2 1 nvsram control slave address command reg address command byte (asenb/asdisb) p stop condition ss t rwi acknowledge (a) by slave acknowledge (a) by slave notes 20. this is the amount of time it takes to take action on a soft sequence command. vcc power must re main high to effectively reg ister command. 21. commands such as store and recall lock out i/o until operati on is complete which further increases this time. see the specif ic command. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 36 of 41 hardware store cycle parameter description cy14x512i unit min max t phsb hardware store pulse width 15 ? ns figure 44. hardware store cycle [22] ~ ~ hsb (in) hsb (out) rwi hsb (in) hsb (out) rwi t hhhd t store t phsb t delay t lzhsb t delay t phsb hsb pin is driven high to v cc only by internal 100 k : resistor, hsb driver is disabled sram is disabled as long as hsb (in) is driven low. write latch not set write latch set note 22. if an sram write has not taken place since the last nonvolatile cycle, no autostore or hardware store takes place. [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 37 of 41 ordering code definitions ordering information ordering code package diagram package type operating range cy14b512i-sfxi 51-85022 16-pin soic industrial cy14b512i-sfxit the above part is pb-free. this table contains final information . contact your local cypress sales representative for availabil ity of these parts. option: t - tape and reel blank - std. density: 512 - 512 kb cypress cy 14 b 512 i - sf x i t 14 - nvsram package: sf - 16-pin soic temperature: i - industrial (-40 to 85 c) i - serial (i 2 c) nvsram with rtc voltage: c - 2.5 v b - 3.0 v e - 5.0 v pb-free [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 38 of 41 package diagram figure 45. 16-pin (300 mil) soic, 51-85022 51-85022 *c [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 39 of 41 acronyms document conventions units of measure acronym description bcd binary coded decimal cmos complementary metal oxide semiconductor crc cyclic redundancy check eia electronic industries alliance i 2 c inter-integrated circuit bus i/o input/output jedec joint electron devices engineering council nvsram nonvolatile static random access memory oscf oscillator fail flag rohs restriction of hazardous substances r/w read/write rwi read and write inhibited scl serial clock line sda serial data line snl serial number lock soic small outline integrated circuit symbol unit of measure c degrees celsius hz hertz kbit 1024 bits khz kilo hertz k ? kilo ohms ? a micro amperes ma milli ampere ? f micro farad mbit/s mega bit per second mhz mega hertz ? s micro seconds ms milli seconds ns nano seconds pf pico farad v volts ? ohms w watts [+] feedback
cy14c512i cy14b512i, CY14E512I document #: 001-64879 rev. *b page 40 of 41 document history page document title: cy14c512i, cy14b512i, cy 14e512i, 512-kbit (64 k 8) serial (i 2 c) nvsram with real time clock document number: 001-64879 rev. ecn no. submission date orig. of change description of change ** 3089747 11/18/2010 gvch new datasheet *a 3201531 03/21/2011 gvch updated autostore operation (description). updated hardware store and hsb pin operation (added more clarity on hsb pin operation). updated table 6 (product id column). updated setting the clock (description). updated figure 37 (changed c1, c2 values to 12 pf, 69 pf from 10 pf, 67 pf respectively). updated register map detail table (?w? bit description). updated best practices . updated rtc characteristics (added t rtcp parameter to the table). updated nvsram specifications (t lzhsb parameter description). fixed typo error in figure 41 . updated in new template. *b 3248510 05/04/2011 gvch datasheet status changed from ?preliminary? to ?final? [+] feedback
document #: 001-64879 rev. *b revised may 4, 2011 page 41 of 41 all products and company names mentioned in this document may be the trademarks of their respective holders. cy14c512i cy14b512i, CY14E512I ? cypress semiconductor corporation, 2010-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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